Input-output organization

CPU initializes DMA Controller by sending memoryaddress and the block size(number of words)

CPU bus signals for DMA transfer
ABUS Address bus High-impedence
Bus request BR DBUS Data bus (disabled)
CPU  when BG is
Bus granted BG ^RD Read
WR Write enabled
Block diagram of DMA controller
Address bus
Data bus Data bus Address bus
buffers buffers Contains the address to
specify the desired location in memory, incremented after each word is transferred
DMA select DS Address register
Register select RS
Read RD Word count register Decremented by one after Write WR Controllogic each word is transferred
and tested for zero
Bus request BR Control register
Bus grant BG
Interrupt Interrupt DMA request
DMA acknowledge ^{to I/O device}
Direct Memory Access

DMA I/O OPERATION

The DMA is initialized by the CPU. The CPU initializes the DMA by sending the following information through the data bus: The starting address of memory block where data are available (for read) or where data are to be stored (for write). The word count, which is the number of words in the memory block. Control to specify the mode of transfer such as read or write. A control to start the DMA transfer (GO command) Upon receiving a GO Command DMA performs I/O operation.

Direct Memory Access