Input-output organization


Each bit is associated with an Interrupt Request from different Interrupt Source - different priority level



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Each bit is associated with an Interrupt Request from different Interrupt Source - different priority level

  • Each bit can be cleared by a program instruction

  • Mask Register:

    • Mask Register is associated with Interrupt Register

    (Control the status of each interrupt request.)

      • Each bit can be set or cleared by an Instruction

      • can be programmed to disable to lower-priority interrupt while a higher-priority device is being serviced. (vice-verso opposite.)

    Priority Interrupt

    INTERRUPT PRIORITY ENCODER

    The priority encoder is a circuit that implements the priority function. If two or more input arrives at the same time, the input having the highest priority will take precedence.
    Priority Encoder Truth table
    D= don’t care
    O utputs conditions x y IST I0 has the
    1 d d d 0 0 1 highest priority
    0 1 d d 0 1 1
    0 0 1 d 1 0 1 x = I0' I1' IST is set one
    0 0 0 1 1 1 1 y = I0' I1 + I0’ I2’ only when one 0 0 0 0 d d 0 (IST) = I0 + I1 + I2 + I3 or more input

    are equal to one.
    The output of the priority encoder is used to form part of vector address for each interrupt source.

    Priority Interrupt

    INTERRUPT CYCLE


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