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№3/2021 year
Technical science and innovation
150
𝐶
par
𝑅
in dif
=
250 ... 500 ns. This time constant will have a particularly harmful effect during
the transition from a large differential current of one sign to a small differential current of the
other sign when the exponential transient process of the voltage rise at the comparator input to
zero voltage can last (7 ... 9)
𝐶
par
𝑅
in dif
. Indeed, the exponential process, which occurs with
the time constant
RC
, is established with an error of 10% for a time equal to 2.3
RC
, with an
error of 1% - for 4.6
RC
, with an error of 0.1% - for 6.9
RC
, with an error of 0, 01% - for 9.2
RC
,
etc. It is easy to see that for a 12-bit DAC and the adopted time constant
𝐶
par
𝑅
in dif
this time
can be reached 2 ... 4 μs, which means the appearance in the total time of one iteration of an
additional component, which has the meaning of some "dead" for the time comparator, which
will significantly increase the conversion time of the ADC with an acceptable static error.
To reduce the harmful effect of this time constant, a resistor
R1
with a resistance of
usually 1 kOhm is connected in parallel with the diode limiter, which by an order of magnitude
reduces the indicated time constant and its harmful effect. However, in this case, it will add its
own delay, which in high-speed ADCs must be taken into account in the total conversion time.
Taking the resistance of this resistor as the initial differential resistance of the
comparator, it is easy to see that the sensitivity of the comparator for the 12-bit ADC under
consideration should be on the order of 0.5 mV. This means that when calculating the time of
one iteration, it is necessary to use its turn-on time corresponding to an overexcitation of 50 ...
100 μV. If, for example, for an integrated comparator 521СА3, which is suitable for a given
ADC in terms of its sensitivity, this time is approximately 0.5 μs instead of 300 ns with an
overexcitation of 5 mV, then the time of one iteration, in this case, taking into account what has
been said, is
𝑡
i
≅
1.0 μs, and the total time of one conversion will be approximately 12 μs for
the implementation of all 12 bits.
The total static error of the ADC under consideration is due to the static error of the
DAC, which is the comparator error. It should be borne in mind that there is no component of
the error generated by the common-mode signal in the comparators operating in the current
comparison mode. To reduce the error caused by the input current, the inverting input of the
comparator is connected to the ground bus through the resistor
R2
, the resistance of which (~ 1
kOhm) should be approximately equal to the output resistance of the DAC.
A feature of the considered 12-bit ADC is the use of a special LSI as its digital part,
which implements the algorithm of successive approximations and is usually called the register
of successive approximations. An example of such as LSI, which has become widespread, is an
IC of the AM2504 type from AMD (USA), made using CMOS technology and compatible with
TTL circuits, as well as an IC of the K155IR17 type.
Based on considered 12-bit DAC and the successive approximation register, it is also
possible to construct 10- and 8-bit ADCs of successive approximations, which are
distinguished by high speed. For example, for an 8-bit ADC with the same input signal range,
the resolution will be 2mV (if you discard the 4 low-order bits of a 12-bit DAC). This allows
the use of a faster comparator type 521CA2 in the converter, which, when overexcited on the
order of 2 mV, has a turn-on time of approximately 120 ns. Also, the settling time of an 8-bit
DAC with an error of 0.5 ... 0.2 EMP is reduced to 100 ns compared to the same time for 12
bits. Thus, taking into account 30 ns for the operation of the successive approximation register,
the time of one iteration of an 8-bit ADC can be chosen equal to
𝑡
i
≅
250 ns, then the total
time of one conversion will be ~ 2 μs.
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