The modified Harvard architecture
from the program memory, one to read the coefficients and one to read the signal value. The final write instructions can be eliminated by using a different technique referred as modulo addressing. An example of a processor that uses this architecture is Motorola DSP5600x . Yet another alternative to the one proposed above is to use fast memories that support multiple, sequential accesses per instruction cycle over a single set of buses. There are processors with one-chip memories that can complete an access in one half of an instruction cycle. Such processors when combined with the Harvard architecture will be able to make four accesses in one instruction cycle.
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