Publications prior to year 2000 are listed below



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Publications prior to year 2000 are listed below:


Dissertation, Book Chapters, and Tutorial Notes


  1. T.Mangir, Submicron Device Modeling & Simulation, Reports to Xerox Corporation, Xerox Parc & Microelectronics Center, 1982-1999

  2. Mobile and Personal Computing and Communication: Wireless via Satellite, Invited, Microwave & Wireless Journal, 2/98

  3. "An Experiment in Transfer of Technology in Networks and Communications," Proceedings of NASA Technology 2006, October 1996

  4. "Reliability and Availability in Client/server Environments," Proceedings of IEEE Wescon Applications Conference, October 1996. (Invited –To appear)

  5. "Reliability and Availability in Client/Server Environments," Proceedings of Applications in Computers and Communications, October 1996. To appear (Invited, reviewed)

  6. "ATM Technology in Computing," Proceedings of Applications in Computer and Communications, WESCON, October 1996. To appear (Reviewed)

  7. "Wireless via Satellite: Communications Systems for Personal/Mobile Communication and Computations," to appear in Journal of Applied Microwave and Wireless (Invited, Reviewed).

  8. "Software Reliability Models," Presentation to Hughes, August, 1996

  9. "The Workshop Problem: Telemedicine System Design," Presentation Notes, IEEE Conference on High Speed Interconnections in Digital Systems, May 1996. (Reviewed)

  10. "The Telemedicine Design Challenge " IEEE Conference on High Speed Interconnections in Digital Systems, Working Group Notes, May 1996. (Reviewed)

  11. "Techniques for Network Integrity and Restoration in ATM   LANs," in preparation for submission

  12. "Satellite Communication Systems for Personal/Mobile Communication and Computation," Invited Paper, Proceedings Applications Conference on Communications Technology, WESCON, November 7-10, 1995, San-Francisco, CA. Nov.1995, (refereed).

  13. "The Future of Public Satellite Communications," Invited Paper, Proceedings, IEEE Aerospace Applications Conference, February 1995, pp. 393-404, (refereed)

  14. Workshop Summary, 1994 IEEE Workshop on High Speed Interconnections for Digital Systems, IEEE LEOS Newsletter, Fall 1994

  15. "An Introduction AIX: IBM's UNIX," Tutorial Notes, Fall 1994

  16. "Client/Server Technology: An Overview," presentation and lecture notes, IBM Corporation, Summer 1994

  17. "Client/Server Technology: An Overview," Presentation and lecture notes, IBM Corporation, Summer 1994

  18. "Pacing and Learning in Teacher Education and Teaching," with Gulsun Zeytinoglu of IBM, World Assembly of International Council on Education for Teaching, July 1994, Istanbul, Turkey.  ICET Conference Record, pp.37

  19. "Teacher's Role as a Guide for Learning to Learn," World Assembly of International Council on Education for Teaching, July 1994, Istanbul, Turkey. ICET Conference Record, pp.12

  20. "Overview of Multichip Module Technology for Packaging of High Speed Digital Systems," 1994 IEEE Workshop on High Speed Interconnections for Digital Systems, May 22-26, 1994, Santa Fe, NM

  21. "Design Considerations for a Photonic Interconnection System," Private Report, June-July 1993, Palo Alto, CA

  22. "Application Characteristics and Requirements for High Speed Digital Systems," Tutorial Notes, 1993 IEEE Workshop on High Speed Interconnections for Digital Systems, May 23-27, 1993, Santa Fe, NM

  23. " Low Cost Networked Ground Stations," Research Report to DOD and NASA, 1992, TRW, No: 92228306. (Also developed a short Videotaped Demo will make available upon request.)

  24. "Low Cost Ground Station Projects," Invited Presentation, DOD Integrated Satellite Control Systems Conference, Aerospace Corporation, El Segundo, CA, November 1992

  25. Commercial and International Satellite Systems, An Overview and Interface to Computer Networks, TRW, pp.23-1992

  26. "Commercial Satellite Networked Ground Stations," Tutorial, Ground Stations Conference, TRW Space and Technology Group, 1992, pp. 23-75

  27. "Defect and Fault-Tolerance in VLSI and WSI Systems," Editor with Professor Maria-Giovanna Sami of Polytechnico de Milano, Italy and Gabrielle Saucier of Nacional Polytechniques de Grenoble, France, Plenum Publishers, 1991

  28. On-Board Processing, Tutorial, TRW 1989

  29. "Effect of Interconnections on Chip Architectures on Designing Very Large Scale, VLSI, and Wafer Scale, WSI, Systems," Part 1 in Wafer Scale Integration, Earl Schwarzlander (Ed.), Kluwer Publications, 1989

  30. Fault-Tolerant Design Techniques for Digital Systems, Tutorial, TRW, 1987

  31. "An Approach to Fault- Tolerant Design of WSI FFT Processor," with Hideki Mori, Special Issue of Real Time Systems, Ed. Stankovic, 1987

  32. T.Mangir, Self Organizing and Self-Repairing Wafer Scale Integration,. IEEE, Workshop on High Density and High Reliability Microelectronics, 1987

  33. "Design for Testability and Diagnosis", NATO Advanced Studies Institute, July 1987, Como, Italy

  34. "Yield Modeling for WSI: A State Report", WSI Workshop Proceedings, March 1987 (Eds.) G. Saucier & J. Trilhe, North Holland

  35. "Impact of Behavior and Dependent Failures on WSI Yield Models", IFIP Conference on WSI (invited presentation), 17-19 March, 1986, Grenoble, France

  36. Mangir, T.E. "Fault Tolerant Design and Wafer Scale Integration," Notes for IEEE Tutorial. IEEE Computer Society, l985

  37. Mangir, T.E. "Applications of AI and Expert Systems to Logic Design," in E.Horbst (ed.) Advances in CAD for VLSI, North Holland, 1985

  38. Mangir, T.E. "Expert System Applications to VLSI CAD and CAT", Notes for IEEE Tutorial. IEEE Computer Society, l984. (Also published as a STEP-84 Monogram by Technological University of Helsinki, Finland, 1984.)

  39. Mangir,T.E. "Use of on Chip Redundancy for Fault-Tolerant VLSI Design," Ph.D. Dissertation, UCLA, June 1981. Also published as a Technical Report of Computer Science Department, CSD 8202O1, University of California, Los Angeles, February 1982. (Also published as a research monograph by Kluwer Publications, Professor Jonathan Allen (of MIT) Consulting Editor, 1982).


Refereed Articles 

  1. Duran, J., Mangir, T.E.,  " Application of Signature Analysis to the Concurrent Test of Microprogrmmed Control Units," Microprocessing and Microprogramming, Special Issue on fault-tolerance, Vol. 20, pp.309-322, 1987

  2. Mangir, T.E. "Sources of Failures and Yield Improvement for VLSI and Restructur­able Interconnects for RVLSI and WSI: Part II   Restructurable Interconnects for RVLSI and WSI," Proceedings of the IEEE Vol. 72, no. 12,pp. l687 1694, December 1984 (invited).

  3. Mangir, T.E. "Sources of Failures and Yield Improvement for VLSI and Restructur­able Interconnects for RVLSI and WSI: Part I   Sources of Failures and Yield Improvement for VLSI," Proceedings of the IEEE vol. 72, no. 6, pp. 690-709, June 1984 (invited)

  4. Mangir, T.E. and Avizienis, A. "Fault Tolerant VLSI Design: Effect of Interconnect Requirements on Yield Improvement of VLSI Designs," IEEE Transactions of Computers, Vol.72, no. 6, pp.690-709, 1982

Refereed Articles in Conference Proceedings


  1. "Design of a Microprogrammed Control Unit with Built-in-Self-Test" with J. Duran, Special issue Mini-Micro Systems on Fault-Tolerant Design, 1987

  2. "Revisiting the Negative Binomial Distribution for the Modelling of Dependencies in Manufacturing of VLSI Circuits," International Conference on Defect and Fault-Tolearance of VLSI Systems, Nov. 5-8, 1990, Grenoble, France.

  3. "Interconnect Technology Considerations for the WSI of a Parallel 2-D FFT Algorithm," International Conference on Defect and Fault-Tolerance of VLSI Systems, Nov. 5-8, 1990, Grenoble, France.

  4. "Fault-Tolerant Wafer Scale Architecture for Variable Point FFT and Signal Processing," with Hideki Mori, July 1989, Como, Italy.

  5. "Two Dimensional Wafer Scale Systolic Arrays for FFT," 3rd International IFIP Workshop on Wafer Scale Integration, June 1989, Orlando, FL. (Invited).

  6. "WSI Yield Modelling: Myth vs. Reality: Impact of Redundancy on VLSI/WSI Yield," Panel member, Design Automation Conference, 29 June- 2 July 1986, Las Vegas, N. (Invited)

  7. Mangir, T.E., Lam, A., and Luong, H. "An Interactive Tool for VLSI Testability Analysis Based on Fault Detection Probability," IEEE International Conference on Computer Aided Design, Santa Clara, CA, November 1984.

  8. "Fault Tolerance Issues in the Implementation of Wafer Scale (WSI) Systems," Panel Presentation, IEEE Fault  Tolerant Computing Symposium, FTCS 14, Orlando, FL, June 1984.     

  9. Mangir,T. E. "Interconnect Technology Issues for Testing and Reconfiguration of WSI," Proc. of IEEE 1984 VLSI In Computer Design, 1984.

  10. Mangir,T. E. and Raghavendra, C. S. "Issues in the Implementation of Fault Tolerant VLSI and Wafer Scale Integrated Systems," Proc. of IEEE VLSI In Computer Design, 1984

  11. Mangir,T.E. and Raghavendra, C. S. "On the VLSI Implementation of Fault-Tolerant Architectures", Proceedings of IEEE ICCD 84:VLSI in Computer Design, Port Chester, NY, Oct 31 Nov 3, 1983.

  12. Mangir, T.E. "Impact and Limitations of Interconnect Technology on VLSI and Restructurable VLSI Design", Proceedings of the IEEE ICCD 83:VLSI in Computer Design, Oct. 31 Nov 3,1983,Port Chester, NY.

  13. Duran,J. and Mangir, T.E. "A Design Approach for a Microprogrammed Control Unit With Built-in Self Test", Proceedings of IEEE Workshop on Microprogramming, MlCR0 16, Pennsylvenia, Oct 11 14,1983.

  14. Mangir, T.E. "Design for Testability: An Integrated Approach to VLSI Testing," Proc. IEEE International Conference on Computer Aided Design, ICCAD 83, Santa Clara, California, Sept. 1983.

  15. Mangir, T.E. and Avizienis, A. "Effect of Interconnect Requirements on the Yield Improvement of VLSI Circuits," Proc. IEEE Compcon 81, pp.322 326, San Francisco, February 1981.

  16. Mangir, T.E. "Fault Modes and Their Effect on Chip Design," Proc. IEEE Interna­tional Conference on Circuits and Computers, ICCC 1980, pp.685 687, New York, October 1980.

  17. Mangir, T.E. and Viswanathan, C.R. "Impact of Semiconductor Technology on Microcomputer Architecture," Proc. International Sym­posium on Mini and MicroComputers, Zurich, Switzerland, June 1978.

  18. Mangir, T.E. "A Modular Multi Microcomputer System," Proc. International Sym­posium on Mini and MicroComputers, pp. l72 175, Zurich, Switzerland, June 1975.

  19. Mangir, T.E. " Microcomputer Selection Considerations" Proc. International Sym­posium on Mini and MicroComputers, pp.44 50, Zurich, Switzerland, June 1975. 

Other Publications and Technical Reports:


  1. "Software Reliability Models, " Report to RADC, TRW Defense and Space, 1989

  2. "Reusability Project Study Report, " TRW Defense and Space, 1989

  3. "Rad-Hard 32-bit RISC Processor Design for High Reliability Applications, "Proposal (Funded over $10M) to RADC, May 1988

  4. "Symbolic Space Born Processor Design and Features," Report to NASA Ames Research Center and Symbolic, Inc., March 1988

  5. Mangir, T.E., "Research Summary on Applications of Expert Systems to CAD and CAT of VLSI," ACM Sigart Special Issue 1985

  6. Mangir, T.E., "EXCAT: A Design for Testability System for VLSI," Proceedings of Second VLSI Technology Symposium Taipei, Taiwan, 1985 (Invited)

  7. Mangir, T.E. and Mori, H. " Wafer Scale Systolic Arrays for Parallel FFT," Proc. International Conference on Signal Processing Applications, Paris, May 1985. (Invited)

  8. Mangir, T.E., "Yield vs. Redundancy for WSI," Quarterly Research Report to IBM Corporation, January 1985

  9. "A Proposal for a Concerted University lndustry Electronics/ Microelectronics Pro­gram," Turkish National Research Council, Ankara, Turkey, September 1984

  10. "Directions for the National Microelectronics Program: A Proposal for Viable VLSI Designs and Design Tools," Joint Meeting of Swedish University; Industry and Government Representatives), Uppsala, Sweden, August 1984

  11. "Recovery in Distributed Fault Tolerant Systems: Session Introduction", IEEE Distributed Computer Conference, May 1984

  12. Mangir, T.E.," Mixed Mode Simulation for VLSI," March 1981, Internal Report, Xerox Corporation

  13. Mangir, T.E., "Strawman VLSI I/O Controller," March 1981, Internal Report, Xerox Corporation

  14. Mangir, T.E.,"I/O Controller Requirements for Document Processors," February 1981, Internal Report, Xerox Corporation

  15. Mangir, T.E7, " I/O Controller Requirements for Existing Xerox Systems," February 1981, Internal Report, Xerox Corporation

  16. Mangir, T.E.," Chip architecture of Xerox VLSI I/O controller," July 1980, Internal Report, Xerox Corporation

  17. Mangir, T.E.," Requirements of a high bandwidth high speed universal controller for Ethernet," June 1980, Internal Report, Xerox Corporation

  18. Mangir, T.E.," Feasibility of a VLSI I/O Controller, April 198O, Internal Report, Xerox Corporation

  19. Mangir, T.E.," VLSI Design limit J imposed by hot e trapping, August 1979, Internal Report, Xerox Corporation

  20. Mangir, T.E.," High drive, minimum area multiplexed row driver for 128K ROM," August 1979, Internal Report, Xerox Corporation

  21. Mangir, T.E.," Sense amplifier choices for 128K ROM," June 1979, Internal Report, Xerox Corporation

  22. Mangir, T.E., "Organization of 128K VLSI ROM," March 1979, Internal Report, Xerox Corporation

  23. Mangir, T.E.," Design Specifications of 128K VLSI ROM," March 1979, Internal Report, Xerox Corporation

  24. Mangir, T.E.," Comparisons of Various mask programming for 128K VLSI ROM," March 1979, Internal Report, Xerox Corporation

  25. Mangir, T.E.," Process and device modeling of double poly 2 phase CCD's," Febru­ary 1979, Internal Report, Xerox Corporation

  26. Mangir, T.E.," Use of Redundancy for Yield Improvement for VLSI memories," January 1979, Internal Report, Xerox Corporation

  27. Mangir, T.E.," Alpha particle sensitivity of High Density VLSI memories," October 1978, Internal Report, Xerox Corporation

  28. Mangir, T.E.," Design rule suggestions for NSIL III VLSI Technology," September 1978, Internal Report, Xerox Corporation

  29. Mangir, T.E.," Substrate current characteristic of NSIL II devices," September 1978, Internal Report, Xerox Corporation

  30. Mangir, T.E.," Hot electron trapping in short channel enhancement NMOS devices," September, 1978, Internal Report, Xerox Corporation

  31. Mangir, T.E.," Punch thru phenomena in Short Channel VLSI Devices," August 1978, Internal Report, Xerox Corporation

  32. Mangir, T.E. "Air Isolated GaAs MOSFETs with Schottky Barrier Spacings" Technical Report to ARPA on Laser Window Materials, 1972, USC

  33. Mangir,T.E., Lam, A.,and Luong, H., "An Interactive Tool for VLSI Testability Analysis Based on Fault Detection Probability," Technical Report CSD­840060,UCLA

  34. Chen Ellis,G., Mangir,T.E., "Rule Based Generation of Test Structures for VLSI," Technical Report CSD 840059,UCLA

  35. Bouchon,P., Mangir, T.E., "An Intelligent Router for VLSI Design," Technical Report CSD 840058,UCLA

  36. Duran,J., Mangir, T.E. and Lang,T., "Design of a Microprogrammed Control Unit with Built in Self Test," Technical Report CSD 840057,UCLA

  37. Duran,J.,and Mangir, T.E. "A Design Approach for a Microprogrammed Control Unit with Built in Self Test," Technical Report CS~840056,UCLA

  38. Mangir, T.E. and Fuenmayor, M., "Meta-level Control for a DRC Program," Techni­cal Report CSD 840055, UCLA

  39. Mangir, Tulin E. & Soetarman, B. "Control Structures in a Prolog Based Produc­tion System," Technical Report CSD 840054, UCLA

Invited Presentations at Professional Meetings


  1. "Expert Systems for Testing of VLSI: An Overview," IEEE Workshop on Testability (invited), 21-24 April, 1986, Lake Tahoe, NV

  2. "Fault Tolerant Design and Wafer Scale Integration," Tutorial, IEEE Compcon, San Francisco, February 1985. (Invited)

  3. "Expert Systems for CAD," Panel Presentation, IEEE International Conference on CAD, ICCAD 84, Santa Clara, November 1984, (Invited).

  4. "AI Techniques for Test Generation, Design for Testability," IEEE International Test Conference Tutorial, Philadelphia, October 15,1984. (Invited).

  5. "Expert System Applications to VLSI CAD and CAT", IEEE Computer Society, Tutorial Week West, San Francisco, October 4 5, 1984. (Invited)

  6. "Yield vs. Redundancy and Interconnect Density for WSI," Wafer Scale Integration Workshop, Semiconductor Research Corporation, RTI, NC, September 1984. (Invited)

  7. "Expert Systems for CAD," STEP 84, Helsinki University of Technology, Helsinki, Finland, August 1984. (Invited Lecture)

  8. " Fault Tolerance Issues in the Implementation of Wafer Scale (WSI) Systems," Panel Presentation, IEEE Fault  Tolerant Computing Symposium, FTCS 14, Orlando, FL, June 1984

  9. "Integrated Testing Approaches for VLSI and WSI," IEEE Napa Valley Test Workshop, May 1984. (Invited)

  10. " Expert System Applications to CAD and CAT," Tutorial, IEEE COMPCON, February 27, 1984, San Francisco. (Invited)

  11. "Restructurable Interconnections for VLSI and WSI," IEEE International Conference­ on Computer Design ICCD 84: VLSI in Computer Design, Oct 31 Nov 3, 1983, Port Chester, NY. (Invited)

  12. "Design for Testability:An Integrated Approach to VLSI Testing", IEEE Interna­tional Conference on Computer Aided Design (ICCAD 83), Sept.12 15,1983,Santa Clara, CA

  13. "Testing as Part of Fault Tolerant Design" LA Chapter, IEEE Computer Society Meeting, March 1983. (Invited)

  14. "Failure Modes for VLSI and Effect on Fault Tolerant VLSI Design," Joint Meeting IEEE Computer and Reliability Societies, LA Chapter, March, 1983. (Invited)

  15. "Wafer to System Level Requirements for VLSI BIST (Built in Self Test)" IEEE BIST Workshop, March 14 17, 1983, Kiawah Island, SC. (Invited)



Other Invited Technical Presentations:


  1. "Scenarios for Ground System Network and I&T (Integration and Test) of GTE Spacenet Satellite System, " GTE, Colorado, April 1990

  2. "WaferScale FFTs for Signal processing," presentation to RADC, Rome, NY. 1989

  3. "Fault-Tolerance for VLSI and WSI," Invited Video broadcast Lecture at USC, EE-Systems, May 1989. (Invited by Prof. C.S. Raghavendra).

  4. "Considerations for Wafer Scale Design of 2 D Systolic Arrays for FFT," Workshop on Wafer Scale Integration, South Hampton, England, July 1985. (Invited).

  5. "EXCAT: An Expert System for Design for Testability," IEEE Workshop on Design for Testability, Beaver Creek, April 1985

  6. "Expert Systems for VLSI Design: Some Examples," Los Angeles Scientific Center, IBM February 1985. (Invited)

  7. "Interconnections for Reconfiguration and Testing for Wafer Scale Integration," Electrical Engineering and Computer Science Department, University of California, Berkeley, November 1984. (Invited).

  8. "Reconfiguration and Testing for Wafer Scale Integration," CSL, Stanford Univer­sity, November 1984. (Invited)

  9. "Interconnect Technology Issues for Testing and Reconfiguration of WSI," IEEE VLSI in Computer Design Conference, Port Chester, NY, October 1984

  10. "Issues in the Implementation of Fault Tolerant VLSI Architecturs," IEEE VLSI in Computer Design Conference, Port Chester, NY, October 1984

  11. "Expert System Applications to CAD and CAT of VLSI," Southern California AI Society (SCAIS) Meeting, Los Angeles, October 1984

  12. "A Proposal for a Concerted University industry Electronics/ Microelectronics Pro­gram," Turkish National Research Council, Ankara, Turkey, September 1984. (Invited)

  13. "Directions for the National Microelectronics Program: A Proposal for Viable VLSI Designs and Design Tools," Joint Meeting of Swedish University; Industry and Government Representatives), Uppsala, Sweden, August 1984. (Invited).

  14. "Design Techniques for Testable Design of VLSI Chips," UppsalaUniversity, Uppsala, Sweden, August 1984. (Invited Seminar)

  15. "Intelligent CAD Systems for Electronic Design," Nokia Data Corporation, Helsinki, Finland, August 1984. (Invited)

  16. " Current Research Topics in VLSI, WSI and Integrated Design Environments," CSD Archives Seminar, UCLA, 1984

  17. "Recovery in Distributed Fault Tolerant Systems: Session Introduction", IEEE Distributed Computing Conference, May 1984

  18. "Yield and Reliability Improvement for VLSI and WSI," CSD Department Seminar, UCLA, April 1984

  19. "Current Research Topics in VLSI and WSI and Integrated Design Environments," UCLA MCASE presentation TRW, April 1984. (Invited)

  20. "On the VLSI implementation of Fault Tolerant Architectures", ICCD 84:VLSI in Computer Design, Oct 31 Nov.3, 1983, Port Chester, NY

  21. "Impact and Limitations of Interconnect Technology on VLSI and Restructurable VLSI Design", ICCD 84:VLSI in Computer Design, Oct 31 Nov 3,1983,Port Chester, NY

  22. "Concurrently Testable VLSI Architectures for Real Time Applications", Fairchild Palo Alto Research Center, Oct 1983 (Invited)

  23. "Design for Testability: An Integrated Approach to VLSI Testing", International Conference on Computer Aided Design (ICCAD 83), Sept.12 15,1983,Santa Clara, CA

  24. "Microcomputers for Control Applications," Bosphorus Univ. Istanbul, Turkey, September 1982

  25. "Speech Synthesis Techniques," Middle East Technical University, Ankara, Turkey, August 1982

  26. "Fault Tolerant Design of Digital Systems," IBM, San Jose, August 1982

  27. " Design for Testability, on Chip Test Techniques for VLSI," Hughes, EODS, El Segundo, CA, May 1982

  28. "Sources of Failures and Yield Improvement for VLSI Chips," Hughes Research Laboratories, Malibu, CA. April 1982

  29. "Spectrum Analysis Techniques," Hughes Research Laboratories, Malibu, Feb.1982

  30. "Fault Tolerance Techniques for Signal Processing Chips," Rockwell International Microelectronics Center, Anaheim, CA., Feb. 1982

  31. "Use of on Chip Redundancy for Fault Tolerant VLSI," Bell Telephone Laboratories, Naperville Ill., Andover, Mass., Murray Hill, N.J. January 82



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