operations
Input/Output Interfaces
I/O INTERFACE
Port A I/O data register
Bidirectional Bus data bus buffers
Port B I/O data register
CPU Chip select CS I/O
Register select RS1 Timing registerControl Control Device
Register select RS0 and
I/O read RD Control Status Status
I/O write WR register
The I/O data to and from CS RS1 RS0 Register selected0 x x None - data bus in high-impedence the device can be 1 0 0 Port A register
transferred into either 11 0 1 Port B register 1 0 Control register
port A or port B. 1 1 1 Status register
T he transfer of data, control, or status information is via a common data bus. The distinction between data, control, or status information is determine from the particular interface register with which the CPU communicates.
Asynchronous Data Transfer
ASYNCHRONOUS DATA TRANSFER
|
Synchronous and Asynchronous
Transfer Operations
Synchronous –
All devices derive use the timing information from common
clock line
Asynchronous –
No common clock used. All devices derive use timing information from own clock.
|
ASYNCHRONOUS DATA TRANSFER
|
Asynchronous Data Transfer
Asynchronous data transfer between two independent units requires that control signals be transmitted between the communicating units to indicate the time at which data is being transmitted.
|
Do'stlaringiz bilan baham: |