The project in SystemVerilog

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The project in SystemVerilog

In Vivado, we say File → New Project ... Select the RTL project as the project type, check the box that does not specify sources at this time. Find Arty in the list in the Board Type Select dialog box.

First, add the previously downloaded XDC file to the project. Copy it to the project directory. Then we say File → Add sources… → Add or create restrictions → Add files, find a copy of the file, click Finish. No matter what you name the Arty_Master.xdc file or a copy of it, the project in the Restrictions group will appear in the file tree (Sources). Open it and do not comment on all the rows in the "Clock" signals, "Switches" and "LED" groups.

Next, we say File → Add Sources… → Add or Create Design Sources → Create File. In the file type, select SystemVerilog, enter something like hello in the file name. We say finish. The Module Identification window then appears, prompting you to click on the module interface. The dialog box is useless because it is easier to execute the same code in the code, so click Cancel.

Find the new file in the Source tree, which will be in the Design Sources group. Open and type the following code:

`time measurement 1ns / 1ps

module salom (

input logic CLK100MHZ,

input logic [3: 0] sw,

output logic [3: 0]


always @ (posedge CLK100MHZ)


if (sw [0] \ u003d \ u003d 0)


LED <= 4 "b0001;

the end



LED <= 4 "b0000;

the end

the end


If everything is done correctly, it will be similar to your Vivado at this stage (clickable, PNG, 71 Kb):

The development of the program is carried out in two stages - synthesis and implementation. In the synthesis phase, the program turns into an abstract scheme of logical doors and other elements. At the implementation stage, a decision is made on how to turn this circuit into an additional device.

Let's say Stream → Start Synthesis or just do the synthesis by pressing F11. In the top right corner you will see that the process is in progress. This can take a long time depending on your computer and the complexity of the program. On my laptop, the synthesis of the above program was completed in about 10 seconds, if now we say Flow → Open Synthesized Design, then you can see such a beautiful picture:

It’s time to shine our board. We say Stream → Run Implementation, then Create Stream → Bitstream. We connect the board to the computer via USB, say Vivadoda Leak → Open Hardware Manager → Open Target → Automatic Connection → Software Device. You need to specify the path to the bit file. I had this:


We call it Software. If the SW0 button is off, the LD4 LED on the board will now light up (see picture on the board above). If the switch is on, the LED turns off. Really simple, but it’s “hello, world”, what were you waiting for? :)


Simulation is the virtual execution of code in Verilog or VHDL directly on your computer, without any FPGAs. This is a unique basis for covering both debugging tool and code with tests.

When I was introduced to the simulation, the first thing I discovered was that it didn’t work for me. The logs were simple:

Error: The created C file was not compiled [...] xsim_1.c.

Google found all sorts of nonsense in this error, such as "try disabling your antivirus." Finally, adding the -v 2 flag to the ~ / opt / xilinx / Vivado / 2017.2 / bin / xelab script helped solve the problem. With his help, I learned that the Clang that pulls the Vivado binary would crash with the following error:

/ a / long / path / to / clang: Error loading public libraries: Cannot open public object file: No such file or


And this error and its solution are already described in the Arch Wiki. Personally, I downloaded an already existing file from the Vivado_HLS directory:

cp ~ / opt / xilinx / Vivado_HLS / 2017.2 / lnx64 / tools / gdb_v7_2 / \\

~ / opt / xilinx / Vivado / 2017.2 / lib / lnx64.o /

... then everything worked. So now, in fact, the simulation example.

Similar to how we created before, create a new file in the Simulation Sources group. Write the following code in the file:

`time measurement 1ns / 1ps

module hello_sim ();

logical clck_t;

logic [3: 0] sw_t;

logic [3: 0] led_t;

Hello _t (clck_t, sw_t, led_t);

initial start

clck_t <= 0;

sw_t <= 4 "b0000; # 1; clck_t <= 1; # 1; clck_t <= 0; # 1;

confirmation (led_t \ u003d \ u003d \ u003d 4 "b0001);

Sw_t <= 4 "b0001; # 1; clck_t <= 1; # 1; clck_t <= 0; # 1;

confirmation (led_t \ u003d \ u003d \ u003d 4 "b0000);

the end


Right-click the file in the Source tree, select Source Node Properties. Remove the Synthesis and Implementation boxes in the Used section. We don’t want any tests that block a place away from the rubber FPGA, do we?

Now we say Flow → Run Simulation → Run Behavioral Simulation. As a result, you will see something similar:

Express translates and optimizes VHDL descriptions into an internal format equal to the level of the primary doors. This format is then compiled in FPGA technology.

To work with VHDL, you need to be familiar with the following concepts:
Hardware description languages.
Using FPGA Express.
Design process model.

The U.S. Department of Defense developed VHSIC HDL (VHDL) as part of the Ultra High Speed ​​\ u200b \ u200bIC Development (VHSIC) program. VHDL describes the operation, functions, input and output of a digital electron. VHDL is similar to modern programming languages ​​in terms of style and syntax, but it includes many hardware-specific constructions. FPGA Express reads and analyzes supported VHDL syntax.
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