Transistor Logic (ttl)

Transistor - Transistor Logic (TTL)

• For input low, i.e. vi = 0.2 V
• Current iR = iRi flows out E of Q1 into inverter driving the input.
• Q2 is in cutoff since it gets almost no base current.
• Q3 is in cutoff since it gets no base current from Q2.
• Why?
• Output is high since iC3 ≈ 0 since Q3 is off.

• +

• +

• +

• _

• +

• _

• _

• _

• VBE1

• VBC1

• VBE2

• VBE3

• VB1

• vi =VCE,sat
• = 0.2V

• +

• _

• iRi

• Low Input, High Output

• vo

• iC3

• Cutoff

• Cutoff

Transistor - Transistor Logic (TTL)

• +

• +

• +

• _

• +

• _

• _

• _

• VBE1

• VBC1

• VBE2

• VBE3

• VB1

• vi =VCE,sat
• = 0.2V

• +

• _

• iRi

• +

• _

• +

• _

• VBE4

• VD

• +

• _

• iR1

• off

• off

• iC2

• iB4

• R1 =
• 1.6 K

• For input low, i.e. vi = 0.2 V
• Output is high since iC3 ≈ 0 since Q3 is off.
• What is the high output voltage? VCC?
• Look at Q4 and diode D.
• Since Q2 is off, iC2 ≈ 0 and so iB4 ≈ iR1
• Then we can write
• How big is iB4 ≈ iR1?
• Since Q3 is off, iC3 ≈ 0 and so iR1 ≈ iB4 ≈ iD ≈ i0 .
• For the output high, the next inverter will have its Q1’s emitter junction reverse biased so i0 ≈ iE1 ≈ 0.
• So iB4 ≈ 0, VBE4 ≈ VD = 0.65 V so

• io

• VCC = 5 V

• vo = HIGH

• n

• p

• R3 =
• 0.13 K

• weakly on

• Low Input, High Output

• iD

Transistor - Transistor Logic (TTL)

• +

• +

• +

• _

• +

• _

• _

• _

• VBE1

• VBC1

• VBE2

• VBE3

• VB1

• vi =VCE,sat
• = 0.2V

• +

• _

• iRi

• +

• _

• +

• _

• VBE4

• VD

• +

• _

• iR1

• off

• off

• iC2

• iB4

• R1 =
• 1.6 K

• In summary, for input low, i.e. vi = 0.2 V
• E junction of Q1 forward biased, so most of iR flows out of E into collector of driving inverter.
• The voltage at the base of Q1 is low, only 0.2 V + 0.7 V = 0.9 V, so the bias for the three junctions in series is only 0.9 V so VBC1 ≈ VBE2 ≈ VBE3 ≈ 0.3 V, which are too low to conduct.
• So Q2 and Q3 are in cutoff.
• Since output is high and connected to a reverse biased E junction for Q1 for the following inverter io ≈ 0
• So iB4 ≈ 0, Q4 and D are weakly on so VBE4 ≈ VD = 0.65 V.
• Very little current is draw by output.
• The output voltage is high.

• io ≈ 0

• VCC = 5 V

• high

• n

• p

• weakly on

• R3 =
• 0.13 K

• Low Input, High Output

• vo = 3.7 V

Transistor - Transistor Logic (TTL)

• +

• +

• +

• _

• +

• _

• _

• _

• VBE1

• VBC1

• VBE2

• VBE3

• VB1

• vi =
• 3.7V

• +

• _

• iRi

• +

• _

• +

• _

• VBE4

• VD

• +

• _

• iR1

• on

• on

• iC2

• iB4

• R1 =
• 1.6 K

• For input high, i.e. vi = 3.7 V
• Output is low since Q2 and Q3 are on. vo = ?
• Since input is high, iE1 ≈ 0 so iC1 ≈ iB2 ≈ iRi.
• Then
• Since there is current flow out C of Q1 into base of Q2 and then into base of Q3, then
• Then
• If Q2 in active mode and β = 10

• io

• VCC = 5 V

• low

• n

• p

• But the base currents for Q2 and Q3 are very large
• and drive these transistors well into saturation.
• Q2 cannot be in active mode since
• ic2R1 = (7.3 mA)(1.6K) = 11.7 V >> VCC!

• R3 =
• 0.13 K

• High Input, Low Output

• iB3

• iB2

• iE2

• iR2

• vo

• iE1 ≈ 0

Transistor - Transistor Logic (TTL)

• For input high, i.e. vi = 3.7 V
• Assuming Q2 and Q3 are on and in SATURATION.
• Then
• Then, since Q2 is in saturation mode, iC2 < β iB2 but VCE2 = 0.2 V and
• Then, assuming Q4 is off, iB4 ≈ 0,
• and
• So Q2 and Q3 are in saturation, and vo = VCE3,sat = 0.2 V.

• +

• +

• +

• _

• +

• _

• _

• _

• VBE1

• VBC1

• VBE2

• VBE3

• VB1

• vi =
• 3.7V

• +

• _

• iRi

• +

• _

• +

• _

• VBE4

• VD

• +

• _

• iR1

• sat

• sat

• iC2

• iB4

• R1 =
• 1.6 K

• io

• VCC = 5 V

• n

• p

• iE2

• iB3

• iR2

• iB2

• R3 =
• 0.13 K

• High Input, Low Output

• off

• VC2

• vo = 0.2V

• R =4 K

• iRo=
• 1.0 mA

• These verify that Q2 and Q3 are in saturation.

Transistor - Transistor Logic (TTL)

• +

• +

• +

• _

• +

• _

• _

• _

• VBE1

• VBC1

• VBE2

• VBE3

• VB1

• vi =
• 3.7V

• +

• _

• iR

• +

• _

• +

• _

• VBE4

• VD

• +

• _

• iR1

• sat

• sat

• iC2

• iB4

• R1 =
• 1.6 K

• For input high, i.e. vi = 3.7 V
• What about our assumption that Q4 was off?
• Since Q3 is in saturation, vo = VCE3,sat = 0.2 V.
• But we know that at B of Q4,
• So
• But we also can write
• So, while Q4’s E junction is forward biased, the bias is not enough to cause much current flow.
• Here is the reason for the diode. Without the diode, Q4 would be on since VBE4 = 0.8 V and Q4 would be in saturation producing a large, undesirable and unnecessary current into Q3.

• io

• VCC = 5 V

• n

• p

• iE2

• iB3

• iR2

• iB2

• VB4

• weakly on

• R3 =
• 0.13 K

• High Input, Low Output

• iRi =
• 0.65 mA

• iRo =
• 1 mA

• vo = 0.2 V

Transistor - Transistor Logic (TTL)

• +

• +

• +

• _

• +

• _

• _

• _

• VBE1

• VBC1

• VBE2

• VBE3

• VB1

• vi =
• 3.7V

• +

• _

• iR

• +

• _

• +

• _

• VBE4

• VD

• vo

• +

• _

• iR1

• sat

• sat

• iC2

• iB4

• R1 =
• 1.6 K

• In summary for input high, i.e. vi = 3.7 V
• E junction of Q1 is reverse biased, so iE1 ≈ 0.
• Current iR (~1 mA) flows out C of Q1 into base of Q2 forcing Q2 into the saturation mode.
• Most of iE2 goes into base of Q3 forcing Q3 into saturation mode
• So vo = VCE3,sat = 0.2 V and the output is low.
• Q4 is only weakly on and not providing much current to Q3
• for the output low (0.2 V) and in the static (unchanging) mode.

• io

• VCC = 5 V

• n

• p

• iE2

• iB3

• iR2

• iB2

• VB4

• weakly on

• iE1

• R3 =
• 0.13 K

• High Input, Low Output

• iRi =
• 0.65 mA

• iRo =
• 1 mA

• vo = 0.2 V