Theme: Expression of signals by time and degree Plan: The Digital Signal Processing

Memory Architectures

It would require to make four accesses to memory in order to implement a simple multiply-accumulate (MAC) instruction, using the von Neumann architecture. The four accesses are made to fetch the instruction, read the signal value, read the coefficient, and write the result. Since the MAC instruction needs to be implemented in one instruction cycle the von Neumann architecture is not suitable for DSP applications in its basic form. With the Harvard architecture two memory accesses can be made in one instruction cycle. If the architecture is modified such that one memory space holds program instructions and data and the other holds data only then we obtain the ‘‘modified’’ Harvard architecture. Thus the four accesses required in the MAC instruction operation can now be achieved with two instruction cycles. The architecture is shown in Figure 8.2 and is used in some DSP processor families such as Analog Devices ADSP21xx . It is also possible to modify the Harvard architecture further and use three memory spaces each with its own set of buses where one space will be used for program and two for data. The processor can then make three independent memory accesses; one to fetch the MAC instruction