|
Acknowledgments. This work was supported in part by the European Union
funded project under the grant M2DC H2020-688201 (
http://www.m2dc.eu/en/
) and
MANGO H2020-671668 (
http://www.mango-project.eu/
).
References
1. Taylor, M.: A landscape of the new dark silicon design regime. In: IEEE Micro,
pp. 8–19, September 2013
2. Nikov, K., Nunez-Yanez, J.L., Horsnell, M.: Evaluation of hybrid run-time power
models for the ARM Big.LITTLE architecture. In: IEEE International Conference
on Embedded and Ubiquitous Computing (EUC), October 2015
250
G. Massari et al.
3. Garcia, R.C., Chung, J.M., Jo, S.W., Ha, T., Kyong, T.: Response time perfor-
mance estimation in smartphones applying dynamic voltage & frequency scaling
and completely fair scheduler. In: IEEE International Symposium on Consumer
Electronics (ISCE), pp. 1–2, June 2014
4. Kwak, J., Choi, O., Chong, S., Mohapatra, P.: Dynamic speed scaling for energy
minimization in delay-tolerant smartphone applications. In: IEEE Conference on
Computer Communications (INFOCOM), pp. 2292–2300, April 2014
5. Park, J.G., Hsieh, C.Y., Dutt, N., Lim, S.S.: Quality-aware mobile graphics work-
load characterization for energy-efficient DVFS design. In: IEEE Symposium on
Embedded Systems for Real-time Multimedia (ESTIMedia), October 2014
6. Srinivasan, S., Kurella, N., Koren, I., Kundu, S.: Dynamic reconfiguration vs.
DVFS: a comparative study on power efficiency of processors. In: International
Conference on VLSI Design and International Conference on Embedded Systems
(VLSID), pp. 563–564, January 2016
7. Egilmez, B., Memik, G., Ogrenci-Memik, S., Ergin, O.: User-specific skin
temperature-aware DVFS for smartphones. In: Design, Automation Test in Europe
Conference Exhibition (DATE), pp. 1217–1220, March 2015
8. Leva,
A.,
Terraneo,
F.,
Giacomello,
I.,
Fornaciari,
W.:
Event-based
power/performance-aware thermal management for high-density microprocessors.
IEEE Trans. Control Syst. Technol. 26, 535–550 (2017)
9. Eyerman, S., Eeckhout, L.: Fine-grained DVFS Using on-chip regulators. ACM
Trans. Archit. Code Optim. 8, 1:1–1:24 (2011)
10. Juan, D.C., Garg, S., Park, J., Marculescu, D.: Learning the optimal operating
point for many-core systems with extended range voltage/frequency scaling. In:
International Conference on Hardware/Software Codesign and System Synthesis
(CODES + ISSS), pp. 1–10. IEEE (2013)
11. Pan, J., Yoshihara, T.: A fast lock phase-locked loop using a continuous-time phase
frequency detector. In: IEEE Conference on Electron Devices and Solid-State Cir-
cuits, pp. 393–396, December 2007
12. Abadian, A., Lotfizad, M., Majd, N.E., Ghoushchi, M.B.G., Mirzaie, H.: A new
low-power and low-complexity all digital PLL (ADPLL) in 180 nm and 32 nm. In:
IEEE International Conference on Electronics, Circuits and Systems (2010)
13. Kim, W., Gupta, M.S., Wei, G.Y., Brooks, D.: System level analysis of fast, per-
core DVFS using on-chip switching regulators. In: IEEE International Symposium
on High Performance Computer Architecture, pp. 123–134, February 2008
14. Altieri, M., Lombardi, W., Puschini, D., Lesecq, S.: Coupled voltage and frequency
control for DVFS management. In: International Workshop on Power and Timing
Modeling, Optimization and Simulation (PATMOS), September 2013
15. Park, S., Park, J., Shin, D., Wang, Y., Xie, Q.: Accurate modeling of the delay and
energy overhead of dynamic voltage and frequency scaling in modern microproces-
sors. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 32, 695–708 (2013)
16. Terraneo, F., Zoni, D., Fornaciari, W.: A cycle accurate simulation framework for
asynchronous NoC design. In: International Symposium on System-on-Chip, SoC
2013 (2013)
17. Begum, R., Werner, D., Hempstead, M., Prasad, G., Challen, G.: Energy-
performance trade-offs on energy-constrained devices with multi-component
DVFS. In: IEEE International Symposium on Workload Characterization (IISWC)
(2015)
18. Tan, L., Chen, Z., Zong, Z., Li, D., Ge, R.: A2E: Adaptively aggressive energy
efficient DVFS scheduling for data intensive applications. In: IEEE International
Performance Computing and Communications Conference (IPCCC) (2013)
Towards Fine-Grained DVFS in Embedded Multi-core CPUs
251
19. Ge, R., Feng, X., Feng, W.C., Cameron, K.W.: CPU MISER: a performance-
directed, run-time system for power-aware clusters. In: International Conference
on Parallel Processing (ICPP), p. 18, September 2007
20.
https://www.kernel.org/doc/html/v4.13/admin-guide/pm/intel pstate.html
21. Leva, A., Terraneo, F., Fornaciari, W.: Event-based control as an enabler for high
power density processors. In: International Conference on Event-based Control,
Communication, and Signal Processing (EBCCSP), June 2016
22. Rodopoulos, D., Catthoor, F., Soudris, D.: Tackling performance variability due
to RAS mechanisms with PID-controlled DVFS. IEEE Comput. Architect. Lett.
14, 156–159 (2015)
23. Liu, Y., Yang, H., Dick, R.P., Wang, H., Shang, L.: Thermal vs energy optimization
for DVFS-enabled processors in embedded systems. In: International Symposium
on Quality Electronic Design (ISQED), pp. 204–209 (2007)
Do'stlaringiz bilan baham: |
