Itu telecommunication Standardization Sector


ITU-T X.85/Y.1321 (03/2001) – Prepublished version



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ITU-T X.85/Y.1321 (03/2001) – Prepublished version 
20


IP-based 
network
DL-UNACK-DATA request
DL-UNACK-DATA indication
SAPI=0021, SAPI=0057
Connection 
Management 
Entity 
MDL-Error indication
Data Link Layer
UITS procedures
PH-DATA indication
PH-DATA request
SDH Physical Layer
FIGURE B.1/X.85/Y.1321 
Primitives Relationship 
ITU-T X.85/Y.1321 (03/2001) – Prepublished version 
21


ANNEX C 
The self-synchronous scrambling/descrambling (x
43
+ 1) function description 
C.1 
The self-synchronous (x
43
 + 1) scrambler/descrambler 
The operation diagram of (x
43
+ 1) self-synchronous scrambler transmitter and receiver (see Figure C.1 and 
Figure C.2) are as follows. XOR is an exclusive-OR gate function. The output bits is exclusive-ored with the 
raw input data bit to produce the transmitted bits. The order of bit transmission within an octet is the most 
significant bit first. The purpose of performing scrambling/descrambling function is to protect correct 
operation of SDH. The performing scrambler and descrambler shall be required for higher order VC-n. The 
C2 byte coding of the high order path signal label is specified (see ITU-T Recommendation G.707) to 
indicate the contents of synchronous payload envelope. It is recommended that "24" (18 hex) is used to 
indicate LAPS with (x
43
+ 1) scrambling. When the LAPS is set to be compatible with RFC2615, the value 
of the SDH path signal label is required to change from 24 (18 hex) to 22 (16 hex). Additionally, the LAPS 
shall also provide the signal label value 207 (CF hex) to indicate PPP without scrambling The V5 byte 
coding of the lower order path signal label is currently not yet defined (see ITU-T Recommendation G.707). 
Scrambling shall be not required for lower order VC-2, VC-12 and VC-11. 
EDITOR'S NOTE - The V5 coding above is to be determined. It is needed to make further liaison statement 
with ITU-T SG 15. 
Unscrambled Data input 
D1
D2
D3
D43 
43-bit shift register 
XOR 
Scrambled Data Output 
FIGURE C.1/X.85/Y.1321 

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