Education of the republic of uzbekistan tashkent state technical university named after islam karimov

Electrical and Computer Engineering
149 
difference in currents 
∆𝐼 = 𝐼
in
− 𝐼
DAC
, where 
𝐼
in
is the current through the resistor 
𝑅
in
, created 
by a positive input voltage. To limit the voltage swing at the comparator input and increase its 
slew rate in this mode, a two-sided diode limiter is used, similar to that used in voltage 
comparators. In order not to decrease the speed of the comparator, these diodes must be fast 
and not have the effect of accumulating minority carriers. Schottky diodes meet these 
requirements best of all. 
Fig. 1. Functional diagram of a 12-bit successive approximation ADC: 1-
reference voltage source; 2- operational amplifier; 3- resistive matrix; 4- 
quadruple analog keys. 
The choice of a comparator for a given ADC is determined by two factors already 
considered: it should provide the required on (off) time with overexcitation, which is 
approximately 0.1 ... 0.2 quantization steps. At a maximum output current of a 12-bit DAC of 2 
mA, its current resolution is approximately 
𝛿𝐼
r
=
0.5 μA. This current creates a voltage drop 
𝛿𝑈
r
= 𝛿𝐼
r
𝑅
in dif
at the input differential resistance of the comparator (the shunting effect of 
diodes at such a current can be neglected), which is the step of quantizing the ADC by voltage. 
The input impedance of the differential stage for the differential signal is variable depending on 
overexcitation. Its minimum value corresponds to the equality of the threshold voltage and the 
signal voltage. For modern integrated bipolar transistor comparators, this resistance is usually 5 
... 10 kOhm. Therefore, reasoning formally, the voltage resolution of the ADC could be chosen 
equal to 
𝛿𝑈
r
=
1 ... 2.5 mV, and based on this value, choose a comparator. 
However, in reality, such a resolution in high-speed ADCs cannot be realized due to the 
parasitic capacitance 
𝐶
par
at the input of the comparator, which is formed primarily by the 
output capacitance of the DAC, as well as the input capacitance of the comparator itself and the 
mounting capacitance. 
Together with 
𝑅
in dif
, this parasitic capacitance determines the time constant 
𝐶
par
𝑅
in dif
, with which the voltage at the input of the comparator rises. Considering that the output 
capacitance of the DAC can reach 40 ... 50 pF, you can see that the specified time constant 

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