Principles of Electronics I

518

 

 

 

 

 

 

 

Principles of Electronics

∴

Gate to source resistance =

9

15 V

10 A

GS

G

V

I

−

=

  =  15 

× 10

9

 

Ω  =  

15,000 M

Ω

Ω

Ω

Ω

Ω

This example shows the major difference between a JFET and a bipolar transistor.  Whereas the

input impedance of a JFET is several hundred M

Ω, the input impedance of a bipolar transistor is only

hundreds or thousands of ohms.  The large input impedance of a JFET permits high degree of isolation

between the input and output.

Example 19.8. 

 When V

GS

 of a JFET changes from –3.1 V to –3 V, the drain current changes

from 1 mA to 1.3 mA. What is the value of transconductance ?

Solution.

ΔV

GS

= 3.1 

− 3  =  0.1 V

... magnitude

ΔI

D

= 1.3 

− 1 =  0.3 mA

∴

Transconductance,  g

f s

=

0.3 mA

3 mA/V

0.1V

D

GS

I

V

Δ

=

=

Δ

  =  

3000 µ mho

Example 19.9. 

 The following readings were obtained experimentally from a JFET :

V

GS

0 V

0 V

− 0.2 V

V

DS

7 V

15 V

15 V

I

D

10 mA

10.25 mA

9.65 mA

Determine (i) a. c. drain resistance (ii) transconductance and (iii) amplification factor.

Solution.  (i)

  With V

GS

 constant at 0V, the increase in V

DS

 from 7 V to 15 V increases the drain

current from 10 mA to 10.25 mA i.e.

Change in drain-source voltage,

ΔV

DS

= 15 

− 7  =  8 V

Change in drain current,  

ΔI

D

= 10.25 

− 10  =  0.25 mA

∴

a.c. drain resistance,  r

d

=

8 V

0.25 mA

DS

D

V

I

Δ

=

Δ

  =  

32 k

Ω

Ω

Ω

Ω

Ω

(ii)

With V

DS

 constant at 15 V, drain current changes from 10.25 mA to 9.65 mA as V

GS

 is

changed from 0 V to – 0.2 V.

Δ V

GS

= 0.2 

− 0  =  0.2 V

Δ I

D

= 10.25 

− 9.65  =  0.6 mA

∴

Transconductance,  g

f s

=

0.6 mA

0.2 V

D

GS

I

V

Δ

=

Δ

  =  3 mA/V  =  

3000 µ mho

(iii)

Amplification factor,  µ = r

d

 

× g

fs

  =  (32 

× 10

3

) 

× (3000 × 10

−6

)  =  

96

19.15 Variation of Transconductance (g

m

 or g

fs

) of JFET

We have seen that transconductance g

m

 of a JFET is the ratio

of a change in drain current (

ΔI

D

) to a change in gate-source

voltage (

ΔV

GS

) at constant V

DS

 i.e.

g

m

=

D

GS

I

V

Δ

Δ

The transconductance g

m

 of a JFET is an important pa-

rameter because it is a major factor in determining the volt-

age gain of JFET amplifiers. However, the transfer charac-

teristic curve for a JFET is nonlinear so that the value of g

m

depends upon the location on the curve. Thus the value of g

m

at point A in Fig. 19.17 will be different from that at point B.

Luckily, there is following equation to determine the value of

g

m

 at a specified value of V

GS 

:

Fig. 19.17

Field Effect Transistors

 

 

    

519

g

m

= g

mo

 

(

)

1

GS

GS off

V

V

⎛

⎞

−

⎜

⎟

⎜

⎟

⎝

⎠

where

g

m

= value of transconductance at any point on the transfer characteristic curve

g

mo

= value of transconductance(maximum) at V

GS

 = 0

Normally, the data sheet provides the value of g

mo

. When the value of g

mo

 is not available, you

can approximately calculate g

mo

 using the following relation :

g

mo

=

(

)

2

|

|

DSS

GS off

I

V

Example 19.10. 

 A JFET has a value of g

mo

 = 4000 

μS. Determine the value of g

m

 at V

GS

 = – 3V.

Given that V

GS (off)

 = – 8V.

Solution.

g

m

= g

mo

 

(

)

1

GS

GS off

V

V

⎛

⎞

−

⎜

⎟

⎜

⎟

⎝

⎠

= 4000 

μS 

– 3V

1 –

– 8V

⎛

⎞

⎜

⎟

⎝

⎠

= 4000 

μS (0.625) = 

2500 

μμμμμS

Example 19.11.

  The data sheet of a JFET gives the following information : I

DSS

 = 3 mA, V

GS

 

(off)

= – 6V and g

m (max)

 = 5000 

μS. Determine the transconductance for V

GS

 = – 4V and find drain

current I

D

 at this point.

Solution.

  At V

GS

 = 0, the value of g

m

 is maximum i.e. g

mo

.

∴

g

mo

= 5000 

μS

Now

g

m

= g

mo

 

(

)

1

GS

GS off

V

V

⎛

⎞

−

⎜

⎟

⎜

⎟

⎝

⎠

= 5000 

μS 

– 4V

1 –

– 6V

⎛

⎞

⎜

⎟

⎝

⎠

= 5000 

μS ( 1/3) = 

1667 

μμμμμS

Also

I

D

= I

DSS

 

2

(

)

1

GS

GS off

V

V

⎛

⎞

−

⎜

⎟

⎜

⎟

⎝

⎠

= 3  mA 

2

4

1

6

−

⎛

⎞

−

⎜

⎟

−

⎝

⎠

=

 333 

μμμμμA

19.16 JFET Biasing

For the proper operation of n-channel JFET, gate must be negative w.r.t. source.  This can be achieved

either by inserting a battery in the gate circuit or by a circuit known as biasing circuit.  The latter

method is preferred because batteries are costly and require frequent replacement.

1.  Bias battery. 

 In this method, JFET is biased by a bias battery V

GG

.  This battery ensures that

gate is always negative w.r.t. source during all parts of the signal.

2.  Biasing circuit.

  The biasing circuit uses supply voltage V

DD

 to provide the necessary bias.

Two most commonly used methods are 

(i)

 self-bias

 (ii) 

potential divider method. We shall discuss

each method in turn.

520

 

 

 

 

 

 

 

Principles of Electronics

19.17 JFET Biasing by Bias Battery

Fig. 19.18 shows the biasing of a n-channel JFET by a bias battery

– V

GG

. This method is also called 

gate bias.

 The battery voltage – V

GG

ensures that gate – source junction remains reverse biased.

Since there is no gate current, there will be no voltage drop

across R

G

.

∴

V

GS

= V

GG

We can find the value of drain current I

D

 from the following

relation :

I

D

= I

DSS

 

2

(

)

1

GS

GS off

V

V

⎛

⎞

−

⎜

⎟

⎜

⎟

⎝

⎠

The value of V

DS

 is given by ;

V

DS

= V

DD

 – I

D

 R

D

Thus the d.c. values of I

D

 and V

DS

 stand determined. The operating point for the circuit is V

DS

, I

D

.

Example 19.12. 

 A JFET in Fig. 19.19 has values of V

GS (off)

 = – 8V and I

DSS

 = 16 mA. Determine

the values of V

GS

, I

D

 and V

DS

 for the circuit.

Solution. 

 Since there is no gate current, there will be no

voltage drop across R

G

.

∴

V

GS

= V

GG

 = 

–

 

5V

Now

I

D

= I

DSS

 

2

(

)

1

GS

GS off

V

V

⎛

⎞

−

⎜

⎟

⎜

⎟

⎝

⎠

= 16 mA 

2

5

1

8

−

⎛

⎞

−

⎜

⎟

−

⎝

⎠

= 16 mA (0.1406) = 

2.25 mA

Also

V

DS

= V

DD

 – I

D

 R

D

= 10 V – 2.25 mA × 2.2 k

Ω = 

5.05 V

Note that operating point for the circuit is 5.05V, 2.25 mA.

19.18 Self-Bias for JFET

Fig. 19.20 shows the self-bias method for n-channel JFET. The re-

sistor R

S

 is the bias resistor.  The d.c. component of drain current

flowing through R

S

 produces the desired bias voltage.

Voltage across R

S

, V

S

= I

D 

R

S

Since gate current is negligibly small, the gate terminal is at

d.c. ground i.e., V

G  

=  0.

∴

V

GS

= V

G

 

− V

S

  =  0 

− I

D 

R

S

or

V

GS

=

− 

*

I

D 

R

S

Thus bias voltage V

GS

 keeps gate negative w.r.t. source.

Fig. 19.18

Fig. 19.19

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*

V

GS

 = V

G

 – V

S

 = Negative. This means that V

G

 is negative w.r.t. V

S

. Thus if V

G

 = 2V and V

S

 = 4V, then V

GS

= 2 – 4 = – 2V i.e. gate is less positive than the source. Again if V

G

 = 0V and V

S

 = 2V, then V

GS

 = 0 – 2 =

– 2V. Note that V

G

 is less positive than V

S

.

Fig. 19.20

Field Effect Transistors

 

 

    

521

Operating point. 

 The operating point (i.e., zero signal I

D

 and V

DS

) can be easily determined.

Since the parameters of the JFET are usually known, zero signal I

D

 can be calculated from the following

relation :

I

D

=

2

(

)

1

GS

DSS

GS off

V

I

V

⎛

⎞

−

⎜

⎟

⎝

⎠

Also

V

DS

= V

DD

 

− I

D

 (R

D

 + R

S

)

Thus d.c. conditions of JFET amplifier are fully specified i.e. operating point for the circuit is

V

DS

, I

D

.

Also,

R

S

=

|

|

|

|

GS

D

V

I

Note that gate resistor 

*

R

G

 does not affect bias because voltage across it is zero.

Midpoint Bias.

  It is often desirable to bias a JFET near the midpoint of its transfer characteris-

tic curve where I

D

 = I

DSS

/2. When signal is applied, the midpoint bias allows a maximum amount of

drain current swing between I

DSS

 and 0. It can be proved that when V

GS

 = V

GS

 

(off) 

/ 3.4, midpoint bias

conditions are obtained for I

D

.

I

D

= I

DSS 

2

(

)

1

GS

GS off

V

V

⎛

⎞

−

⎜

⎟

⎜

⎟

⎝

⎠

 = I

DSS

 

2

(

)

(

)

/ 3.4

1

GS off

GS off

V

V

⎛

⎞

−

⎜

⎟

⎜

⎟

⎝

⎠

 = 0.5 I

DSS

To set the drain voltage at midpoint (V

D

 = V

DD

/2), select a value of R

D

 to produce the desired

voltage drop.

Example 19.13. 

 Find V

DS

 and V

GS

 in Fig. 19.21, given that I

D

 = 5 mA.

Solution.

V

S

= I

D

 R

S

 = (5 mA) (470 

Ω) = 2.35 V

and

V

D

= V

DD

 – I

D

 R

D

= 15V – (5 mA) × (1 k

Ω) = 10V

∴

V

DS

= V

D

 – V

S

 = 10V – 2.35 V = 

7.65V

Since there is no gate current, there will be no voltage drop across R

G

and V

G

 = 0.

              Now

V

GS

= V

G

 – V

S

 = 0 – 2.35V = 

– 2.35 V

Example 19.14.

 

 The transfer characteristic of a JFET reveals that

when V

GS

 = – 5V, I

D

 = 6.25 mA. Determine the value of R

S

 required.

Solution.

R

S

=

|

|

5V

|

|

6.25 mA

GS

D

V

I

=

 = 

800 

Ω

Ω

Ω

Ω

Ω

Example 19.15.

  Determine the value of R

S

 required to self-bias a p-channel JFET with I

DSS

 =

25 mA, V

GS (off) 

= 15 V and V

GS

 = 5V.

Solution.

               I

D

  =  I

DSS

 

2

(

)

1

GS

GS off

V

V

⎛

⎞

−

⎜

⎟

⎜

⎟

⎝

⎠

 = 25 mA 

2

5V

1

15V

⎛

⎞

−

⎜

⎟

⎝

⎠

= 25mA  (1 – 0.333)

2

 = 11.1 mA

∴

R

S

=

|

|

5V

|

|

11.1 mA

GS

D

V

I

=

 = 

450 

Ω

Ω

Ω

Ω

Ω

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*

R

G

 is necessary only to isolate an a.c. signal from ground in amplifier applications.

Fig. 19.21

522