Input-output organization

Output data are always in the same order in which the data entered the buffer.

Useful in some applications when data is transferred asynchronously

Asynchronous Data Transfer

FIRST-IN-FIRST-OUT(FIFO) BUFFER

4 x 4 FIFO Buffer (4 4-bit registers R1,R2,R3,R4), store 4 words of four bits each. A Control Register (flip-flops Fi, associated with each Ri), Fi is set 1 indicates a 4-bit data word is stored in Ri, if Fi=0 means Ri not contain valid data. Control registers direct the movement of data through the registers. Whenever Fi=1 and the Fi+1 bit is reset (Fi’+1=1), a clock is generated C ausing register R(i+1) to accept data from Ri. The same clock sets Fi+1 to 1 and reset Fi to 0. R1 R2 R3 R4 lines

MODES OF TRANSFER - PROGRAM-CONTROLLED I/O -

3 Program-Controlled I/O Interrupt-Initiated I/O Direct Memory Access (DMA) different Data Transfer Modes between the central computer(CPU or Memory) and peripherals; Program-Controlled I/O(Input Dev to CPU) Data bus Interface I/O bus Address bus Data register Data valid I/O CPU I/O read device I/O write Status F Data accepted register R