Fp7 ict work Programme 2009-10 ict

3.1 Nanoelectronics technology Target outcome

• Miniaturisation and functionalisation
• Beyond 22 nm devices, advanced components with lower scaling factors including non-CMOS devices, and
• their integration and interfacing with very advanced CMOS

• Activities with a high risk factor

• Industrialisation perspective beyond 2014 and
• having a generic development focus

• Funding schemes:
• STREPs
• NoE

3.1 Nanoelectronics technology Target outcome

• Miniaturisation and functionalisation – STREPs
• Increasing process variability and expected physical and reliability limitations of devices and interconnects;
• The need for new circuit architectures, metrology and characterisation techniques;
• Interface and system integration technologies on a single silicon chip (SoC) and/or integration of different types of chips and devices in a single package (SiP);
• New device structures for non-Si and Si based advanced integrated components to add functionality to circuits and (sub)systems;
• Disruptive technologies and functional devices beyond the traditional ITRS shrink path (‘Beyond CMOS’): new non-CMOS logic, analogue and memory devices, and their integration in and/or interfacing with CMOS
• Specific issues: electromagnetic interference, heat dissipation, energy consumption

3.1 Nanoelectronics technology Target outcome

• Miniaturisation and functionalisation – NoE
• The merging of ‘Beyond CMOS’ and advanced ‘More than Moore’ devices and processes to create CMOS backbone, to meet the challenge of
• the increasingly analogue behaviour of ‘Beyond CMOS’ devices and
• systems partially based on new architectures and on less reliably functioning devices.

• 1 NoE is expected
• Budget: 3 M€