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110r aaaa aaaa aaaa
Use address bits A[35:24] for future requests.
1110 aaaa aaaa aaaa
Use address bits A[47:36] for future requests.
1111 0xxx, 1111 10xx, 1111 110x
Reserved, do not use.
1111 1110
Synchronization pattern used when starting the SBA bus after an idle period.[11]: 68 [13]: 163
1111 1111
No operation; no request. At AGP 1× speed, this may be sent as a single byte and a following 16-bit side-band request started one cycle later. At AGP 2× and higher speeds, all side-band requests, including this NOP, are 16 bits long.
Sideband address bytes are sent at the same rate as data transfers, up to 8× the 66 MHz basic bus clock. Sideband addressing has the advantage that it mostly eliminates the need for turnaround cycles on the AD bus between transfers, in the usual case when read operations greatly outnumber writes.
AGP responses[edit]
While asserting GNT#, the motherboard may instead indicate via the ST bits that a data phase for a queued request will be performed next. There are four queues: two priorities (low- and high-priority) for each of reads and writes, and each is processed in order. Obviously, the motherboard will attempt to complete high-priority requests first, but there is no limit on the number of low-priority responses which may be delivered while the high-priority request is processed.
For each cycle when the GNT# is asserted and the status bits have the value 00p, a read response of the indicated priority is scheduled to be returned. At the next available opportunity (typically the next clock cycle), the motherboard will assert TRDY# (target ready) and begin transferring the response to the oldest request in the indicated read queue. (Other PCI bus signals like FRAME#, DEVSEL# and IRDY# remain deasserted.) Up to four clock cycles worth of data (16 bytes at AGP 1× or 128 bytes at AGP 8×) are transferred without waiting for acknowledgement from the card. If the response is longer than that, both the card and motherboard must indicate their ability to continue on the third cycle by asserting IRDY# (initiator ready) and TRDY#, respectively. If either one does not, wait states will be inserted until two cycles after they both do. (The value of IRDY# and TRDY# at other times is irrelevant and they are usually deasserted.)
The C/BE# byte enable lines may be ignored during read responses, but are held asserted (all bytes valid) by the motherboard.
Shuningdek, karta RBF # (buferni to'liq o'qing) signalini vaqtincha kam ustuvor O'qilgan javoblarni qabul qila olmasligini ko'rsatishi mumkin. Anakart har qanday past-ustuvor o'qish javob rejalashtirish tiyilish bo'ladi. Karta hali ham joriy javobning oxirini va agar rejalashtirilgan bo'lsa, quyidagi to'rt tsiklli blokni va shuningdek, u talab qilgan har qanday ustuvor javoblarni olishi kerak.
Gnt# tasdiqlanganda va holat bitlari qiymatga ega bo'lgan har bir tsikl uchun 01p, yozish ma'lumotlar avtobus bo'ylab yuborilishi rejalashtirilgan. Keyingi mavjud imkoniyatda (odatda keyingi soat tsikli) karta irdy# (tashabbuskor tayyor) ni tasdiqlaydi va ko'rsatilgan yozish navbatidagi eng qadimgi so'rovning ma'lumotlar qismini uzatishni boshlaydi. Agar ma'lumotlar to'rt soat tsiklidan uzunroq bo'lsa, anakart uchinchi tsiklda TRDY# ni tasdiqlash orqali davom etish qobiliyatini ko'rsatadi. O'qishdan farqli o'laroq, kartani yozishni kechiktirish uchun hech qanday shart yo'q; agar u yuborishga tayyor ma'lumotlarga ega bo'lmasa, u so'rovni navbatga qo'ymasligi kerak edi.
C / BE# satrlari yozish ma'lumotlari bilan ishlatiladi va karta tomonidan xotiraga qaysi baytlarni yozish kerakligini tanlash uchun ishlatilishi mumkin.
AGP dagi multiplikator 2ta, 4ta va 8ta razryadlar har 66 MGts soat sikli davomida avtobus bo'ylab ma'lumotlar uzatish sonini ko'rsatadi. Bunday o'tkazmalarda ma'lumotlar manbai tomonidan hosil qilingan "strobe" signali (AD_STB[0], AD_STB[1] va SB_STB) bilan manba sinxron xronikasi ishlatiladi. AGP 4o'zgaruvchilarningo'zgaruvchi strobe signallarini qo'shib boradi.
AGP operatsiyalari ikki transfer kabi qisqa bo'lishi mumkin, chunki, AGP da 4 bir soat tsikli o'rtasida bajarish uchun bir so'rov uchun imkon va 8 bir soat aylanishi uchun tezliklar. Bunday holda, davr model ma'lumotlar uzatish bilan padded bo'ladi (C bilan/BE# bayt deasserted bo'lib liniyalari faollashtirish).
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