Computer Architecture (110)

Assembly Instruction
Effect
LOAD R2, B	Copy the contents of memory location designated by B into Register 2
ADD R2, C	Add the contents of the memory location designated by C to the contents of Register 2 and put the result back into Register 2
STORE R2, A	Copy the contents of Register 2 into the memory location designated by A.

Each of these assembly instructions needs to be encoded into binary for execution by the Central Processing Unit (CPU). Let’s try this encoding for a simple architecture called TOY1.

TOY1 Architecture

TOY1 is a fictitious architecture with the following characteristics:

1024 x 16-bit words of RAM maximum. RAM is word-addressable.
4 general purpose registers R0, R1, R2 and R3. Each general purpose register is 16-bits (the same size as a memory location).
16 different instructions that the CPU can decode and execute, e.g. LOAD, STORE, ADD, SUB and so on. These different instructions constitute the Instruction Set of the Architecture.
The representation for integers will be two’s complement.
For this architecture, the architect (us) needs to define a coding scheme²³ for instructions. This is termed the Instruction Format. Lets look at an example before we consider how we arrived at it. Here’s our instruction format for TOY1:
TOY1 Instruction Format

TOY1 instructions are 16-bits (so they will fit into a main-memory word). Each instruction is divided into a number of instruction fields that encode a different piece of information for the CPU.

Field Name Field Width